Analog-to-digital conversion system



Oc't. 3, 1967 osAMu TADA ANALOG-TO-DIGITAL CONVERSION SYSTEM 2Sheets-Sheet z Filed May 2 A TT( )RN E YS United States Patent 3,345,630ANALOG-TO-DIGITAL CUNVERSION SYSTEM Osamu Tada, Tokyo, Japan, assignorto Kahushikikaisha Yolrogawa Denki Seisakusho (Y okogawa Electric WorksLtd), Tokyo, Japan, a corporation of Japan Filed May 2, I963, Ser. No.277,628 Claims priority, application Japan, May 14, 1962, 37/ 19,399 3Claims. (Cl. 340-347) This invention relates to an analog-to-digitalconversion system such that voltages are compared successively, and moreparticularly to a system of this kind in which direct current voltage isconverted into alternating current and the alternating current voltageis compared with a reference voltage.

There has been recently proposed and put into practical use theso-called computer control system in which a digital electronic computeris introduced into a process control. In such a system, in response to aprogram and a selective command signal which have been previouslyincorporated in a computer, analog signals (composed mainly of directcurrent signals of low level in general) to be transmitted fromtransducers provided respectively for detecting temperature, pressure,flow quantity and the like, are sampled by sampling devices andamplified by amplifiers, thereafter they are digitized by an analog-todigital converter and introduced into the computer. In the abovesampling stage and the amplification stage, there have heretofore beensome technical problems to make the system impracticable, some of whichwill hereinbelow be referred to.

There are often troubles due to outside induced noises coming from thetransducers and their transmission lines and due to noises produced inthe switching circuit used in a sampler circuit. The outside inducednoises may be damped by inserting a suitable low-pass filter at thepreceding stage of the sampler circuit. However, the noises to beproduced in the switching circuit, particularly spike voltages due tothe on-and-off operation of transistors when a transistor chopper isused in the switching circuit, result in errors when digitization.Furthermore, a comparator circuit, in principle, must compare signals ofhigh level direct current, and hence if input direct current signals areof low level (for instance 0-10 mv.), a direct current amplifier isnecessary for amplifying the signals up to a high level of, for example0-10 v. However, as a direct current amplifier having a broad bandamplification characteristic from direct current to high frequencyregion there are direct-coupled or modulation type direct currentamplifiers, but the former does not suit for amplification of low levelsignals because it causes drift. The latter, namely the modulation typedirect current amplifiers is composed of cascade circuits such as aDC-AC converter circuit for once converting input direct current signalsinto alternating current signals, an alternating current amplifiercircuit for amplifying the converted alternating current signals and aphase sensitive rectifier for converting once more the amplifiedalternating current output into direct current, and a low-pass filter isalso included in the output side of the phase sensitive rectifier, sothat the response speed between the input and output in the whole directcurrent amplifier is limited of itself. Moreover, the direct currentamplifier must stably amplify the absolute value of the input signal asdescribed above, which requires means for negative feedback of theamplifier output to the input side. If such a negative feedback systemis adopted, it becomes difficult to obtain the direct current out-putsignal in a state of being insulated in direct current from theamplifier. Even if each one end of input and output terminals isgrounded to form the so-called two-point ground so as 3,345,630 PatentedOct. 3, 1967 to overcome such diificulty, various troubles are liable tooccur.

Accordingly, a principal object of this invention is to provide a novelanalog-to-digital conversion system without the above manydisadvantages.

Another object of this invention is to provide a cheap analog-to-digitalconversion system which is simple in circult structure.

Other objects, features and advantages of this invention will becomeapparent from the following description taken in conjunction with theaccompanying drawings, in which:

FIGURE 1 is a block diagram, principle of this invention;

FIGURE 2 is a block diagram illustrating an embodiment of thisinvention;

FIGURE 3 shows timing waveform diagrams illustrating the advance of itsoperation with the lapse of time; and

FIGURE 4 is a partial circuit diagram of a digital-toanalog conversionsystem to be used in this invention.

Referring now to FIGURE 1, it includes in its main part a device fordigitizing peak values of alternating voltages and shows a device forconverting direct current input signals of low level into digital form.1 is a DC-AC converter circuit, 2 an AC amplifier circuit and 3 acomparator circuit. As a comparator circuit, it is advisable to use, forexample a multiar comparator circuit or a Schmitt trigger circuit, inshort the comparator circuit is a circuit in which two voltages arecompared and its result is delivered in the form of an electricalsignal. 4 is a digital-to-analog conversion circuit, and its example isillustrated in FIGURE 4 in which it is composed of combinations of adirect current reference voltage source E and resistance elements R R RR the resistance elements R R R being connected in parallel or in seriesto the resistance elements R respectively through switches S S S Withsuch connection, a reference direct current voltage V which varies stepby step is delivered to a lead line 14. For example, in FIGURE 4, whenobtaining a direct current voltage V corresponding to a digital code ofan n-bit in binary code, the resistance values of the resistanceelements are selected respectively to be such that for explaining theFHJLFRO In this case, R R R R are resistance values of the resistanceelements, where n is any desired positive integer. When moving contactsof the respective switches are all in contact with a stationary contacta as illustrated in FIGURE 4, the circuit is in the so-called clearedcondition and the voltage V is zero. When the moving contact of theswitch S alone is in contact with a stationary contact b and all theother switches are in contact with the stationary contact a, in otherwords, in a state of a first bit circuit 4 being set, it follows that sVP In like manner, when a second bit circuit 4 alone is set and in thecase where an nth bit circuit only is set,

3 corresponding to LSD (least significant digit) is delivered from thenth bit circuit 4 In FIGURE 1, 5 is a pulse generator circuit using amonostable multivibrator circuit and 5 is a gate circuit. 7 is ashift-register circuit composed of a cascade circuit of flip-flopcircuits, which delivers a set pulse to each of respective channels 1717 17 at every shot of incoming clock pulses. Such a shift-registercircuit is well known by those skilled in the art, and hence no furtherdetailed explanation thereon will be made for the sake of simplicity. 8is an alternating current source.

In the device shown in FIGURE 1, when an input direct current signal isimpressed through a lead line 10 to the DC-AC converter circuit 1(direct current-alternating current converter circuit 1) driven by theoutput of an alternating power source 8 through the lead line 11 to itsoutput lead line 12 is delivered an alternating signal of amplitudesynchronizing with the alternating current voltage of the power source 8and in proportion of the amount of the input direct current. Thealternating current signal in the lead line 12 is amplified by thealternating current amplifier 2, thereafter being applied as V through alead line 13 to one input circuit of the comparator circuit 3. On theother hand, to the other input circuit of the comparator circuit isapplied a direct current reference voltage V from the digital-to-analogconversion circuit 4 through a lead line 14.

Suppose that the digital-to-analog conversion circuit 4 has been clearedand the voltage V is Zero at the start of the operation. When a clockpulse P synchronizing with the output alternating current of the powersource 8 is applied from the pulse generator circuit 5 through a leadline 15 to the shift-register circuit 7, the flip-flop circuits of therespective stages are successively set at every shot of the clock pulse,in response to which set pulses P are successively delivered to a leadline 17. In the digital-to-analog conversion circuit 4, a referencevoltage V which varies stage by stage from direct current correspondingto MSD to that to LSD is delivered to the lead line 14 at every shot ofthe set pulse P to be added through the lead line 17. Then, a peak valuee of the alternating current voltage V added to the lead line 13 isdirectly compared with the reference voltage V added to the lead line 14in the comparator circuit 3. In the comparing operation, pulse signals Pare delivered to a lead line 18 when e gV only. The gate circuit 6 doesnot deliver any reset pulse in the presence of the pulse signal P in thelead line 18 and delivers a reset pulse P to a lead line 16 in theabsence of the pulse signal P This operation is a characteristic of thisinvention, so further detailed explanation will be described later on.Thus, the peak value e of the alternating signals V to be applied to thelead line 13 is successively compared with the output V of every bit ofthe circuit 4 at every one cycle of the signal V and then comparisonresults are digitized in response to whether there is the reset pulse Pin the lead line 16 or by a combination of the bit circuits ofrespective stages in the circuit 4.

FIGURE 2 is a block diagram illustrating an example in which the peakvalue of the alternating signal is digitized, which will hereinafter beexplained with reference to the timing waveform diagram shown in FIGURE3.

First, a clock pulse P in a lead line 15 to be introduced into ashift-register circuit 7 is a pulse synchronizing with an inputalternating signal V (FIGURE 3A) to be applied to a lead line 13, whichpulse is produced one by one at a specific phase point (FIGURE 3-B) atevery cycle (its period is T sec.) of V This pulse P is generated by apulse generator circuit 5, which is desired to be coincident in timewith the minus peak of V This is because of the fact that although areference voltage V from a digital-to-analog conversion 4 contains atransient portion T as shown in FIGURE 4-D, it is desired that thetransient portion has terminated at a and the reference voltage hasreached a regular value until a positive half cycle of the voltage V isproduced as will be described latter on. Then, a voltage V and themaximum value e of the voltage. V are compared at the positive peak ofthe voltage V by which the comparison therebetween may easily beeffected. This is the same with pulses P P Flip-flop circuits of therespective stages of a shift-register circuit 7 operate successively atevery impression of the clock pulse P for example a set pulse P isdelivered to a lead line 17 upon a first shot P of the clock pulse(FIGURE 3C and a set pulse P is delivered to a lead line 17 upon asecond shot P (FIGURE 3C In like manner a set pulse P is produced, andthus a set pulse P is delivered to a lead line 17 upon the impression ofan nth clock pulse P 4 4 4 4 show respective bit circuits of thedigital-to-analog conversion circuit 4 as previously explained withreference to FIGURE 4. At first, when the first bit circuit 4 is held bythe set pulse P the reference voltage V is delivered to the lead line 14in response to MSD, and this reference voltage is held by the switch Suntil a reset pulse P is applied. When the second bit circuit 4 is heldby the set pulse P a direct current voltage corresponding thereto isdelivered after added to the voltage V which has existed in the leadline 14 until at that time, namely a voltage V is delivered (refer toFIGURE 3-D). As illustrated in FIGURE 2, the clock pulses P are delayedby a delay circuit D and they are applied to the input side of a circuitFF including a kind of flip-flop circuits so formed as to perform thesame function as that of the shift-register 7. The delay time isselected in a manner so that the pulse I corresponds to the period ofthe half cycle of the voltage V Thus, the circuit FF produces pulses P PP such as shown in FIGURE 3-F F and F in accordance with its respectivechannels ch ch ch Then, by connecting mono-multivibrator circuits M M Mto be operated by these pulses, pulses P P P are produced which are ofcertain width 7' such as shown in FIGURE 3G G and G These pulses areapplied respectively to gate circuits 6,, 6 6 6,, through lead lines 1919 19 19 6 6 6 6 are kinds of logic circuits constituting one part ofthe gate circuit 6 and they form inhibit circuits. The impresion timesof the timing signals P P Ptg P to be added respectively to the leadlines 19 19 19 19 are all different as described above. Referring to thecircuit 6 of the logic circuits 6, this operation will hereinbelow beexplained. Only when a signal P has not ever been applied from a leadline 18 in the presence of the timing signal P on the lead line 19 areset pulse P,, is delivered to the lead line 16 being delayed by acertain period. In other cases the reset pulse is never produced. It ismade so that the aforementioned timing signals P P P P (FIGURE 3-Gthrough G may be produced only for a very short period 1- sec. (T T) inthe neighborhood of the peaks of first, second, and third cycles of theinput alternating signals.

Next, the relationship in time that the input alternating signal V isdigitized by the above instrument will hereinafter be explained. Whenthe first shot pulse P of the clock pulse P synchronizing with the inputalternating signal V to be applied to the lead line 13 enter theshift-resistor 7 through the lead line 15, the set pulse P is deliveredto the lead line 17 and the reference voltage V is produced in theoutput lead line 14 of the circuit 4 in response to the Weight of thefirst bit circuit 4 In this case, the set pulse P is produced at a timecorresponding to the trough of the waves of the alternating signal V asshown in FIGURE 3-0 so that the reference voltage V is compared with thepeaks value e in a stable period after its transient period T (refer toFIG- URE 3-D). If the peak value e of the signal V is larger than thereference voltage V a pulse signal P is delivered to the lead line 18for its period (refer to FIGURE 3-E). For this reason, although thetiming signal P has been applied to the lead line 19 the reset pulse Pis not produced in the output lead line 16 of the logic circuit 6Accordingly, the first bit circuit 4 of the digital-to-analog conversioncircuit 4 remains held.

Then, when the second shot pulse P of the clock pulse P is applied tothe shift-register circuit 7 and the reset pulse P is delivered to thelead line 17 the second bit circuit 4 is held thereby, and a sum V ofdirect current voltages corresponding to the aforementioned MSD and thatcorresponding to the succeeding unit of MSD is delivered to the leadline 14. This reference voltage V is then compared with the peak valueof the second cycle of the alternating signal V In this case, if em V asshown in FIGURE 3-D, the signal P does not appear in the lead line 18within a period of time during which the timing signal P is impressed tothe lead line 19 Hence after a certain period of time a reset pulse P isproduced in the output lead line 16 of the logic circuit 6 (refer toFIGURE 3-H), by which the second bit circuit 4 is released from beingheld. Thereafter, similar comparing operations are succesively carriedout, and with completion of the operation of an nth bit circuit 4 thedigitization of the input alternating signal V is finished. Thisdigitization may be expressed in accordance with the fact whether therespective bit circuits of the circuit 4 are held or not.

It is made that the reset pulse P is produced behind in time from thetiming signal P substantially by a quarter cycle from the positive peakof the alternating voltage V This delay is effected by the delay circuitprovided in the gate circuit 6 Because it is possible that if the resetpulse P is produced in the vicinity of the positive peak of thealternating voltage V for example at a point P and the comparisonvoltage V appears as shown in FIG- URE 3-D, the alternating currentvoltage V is still larger than the voltage V as shown by Q. In thisstate, unnecessary pulses are liable to enter the gate circuit 6 throughthe lead line 18, making the operation of the circuit inaccurate. Toavoid this unnecessary trouble, the reset pulse P is delayed suitably asexplained above.

According to this invention as described above, one bit of the digitalcode corresponds to one cycle of the alternating signal, so that aperiod of ten cycles of an alternating signal is required for effectingconversion of ten bits in, for example binary code. In this case, thepeak value e of the alternating signal V is made not to vary in thisconversion period. Accordingly, it is suflicient merely to raise thefrequency of the alternating signal V so as to shorten the conversionperiod.

As has been described in the foregoing, in the analogto-digitalconversion system of this invention the input alternating signal and thedirect current reference voltage are compared only for a short periodduring which the timing signal is impressed, hence even if a noisesignal is included in the alternating signal V for a period during whichthe above timing signal is not impressed, the noise does not everparticipate in the digitization. For example, in the case where atransistor chopper is used in the DC-AC converter circuit 1, even ifspike noises, for instance N and N in FIGURE 3-A are produced in anon-and-otf changover period of the transistor chopper, in other words,at a phase point where the polarity of a converted alternating signal isinverted, the digital conversion may be effected without being affectedby the noise by shifting the impression period of the timing signal fromthe phase point where the noise occurs. Furthermore, since directcurrent input signals of low level may be converted directly from analogto digital form in the form of alternating current large amplitude afterconverted into alternating current and amplified in the chopper circuit,no synchronous rectifier circuit is necessary, and further a low-passfilter is not required to be provided in its output circuit, so that theresponse between the input and the output may be performed extremelyfaster than in heretofore known systems. As explained above, thealternating current signal is directly used, and hence the input and theoutput may completely be separated with respect to direct current by theuse of a transformer.

It will be apparent that many modifications and variations may beeffected without departing from the scope of the novel concept of thisinvention.

What is claimed is:

1. An analog-to-digital conversion system comprising a shift-registercircuit for successively producing set pulses upon impression of clockpulses synchronized with input alternating signals, a source of theinput alternating signals, a digital-to-analog conversion circuitcoupled to said shift-register circuit for successively producing directcurrent reference voltages in response to the weight of said set pulses,a comparator circuit coupled to said source and said conversion circuitfor directly comparing said direct current reference voltage with thepeak value of said input alternating signal, a gate circuit coupled tosaid comparator circuit and to said source to the input alternatingsignals to be controlled by the output signal of said comparatorcircuit, and means coupled between said gate circuit and said conversioncircuit for re-controlling said digital-to-analog conversion circuitwith the output signal of said gate circuit.

2. An analog-to-digi-tal conversion system of direct current signalscomprising means for supplying input direct current signals a DC-ACconversion circuit driven by, a source of alternating voltages andcoupled to said means for converting said direct current signal to analternating signal, means coupled to said conversion circuit foramplifying said converted alternating signal, means coupled to said ofalternating voltages for generating clock pulses synchronizing with saidalternating signal, a digitalto-analog conversion circuit coupled tosaid means for generating clock pulses and pulses controlled by saidclock pulses, a comparator circuit coupled to said digital-toanalogconversion circuit and to said means for converting for directlycomparing the output direct current of said digital-to-analog conversioncircuit with the peak value of said amplified alternating signal, a gatecircuit coupled to said comparator circuit and to said source ofalternating current voltage controlled by the output signal of saidcomparaator circuit, and means coupled to said gate circuit and saiddigital-to-analog conversion circuit for recontrolling saiddigital-to-analog conversion circuit with the output signal of said gatecircuit.

3. An analog-to-digital conversion system comprising a comparatorcircuit for directly comparing the peak values of an input alternatingsignal with the output direct current signal of a digital-to-analogconversion circuit; a source of the input alternating signal coupled tosaid comparator circuit; a digital-to-analog conversion circuit coupledto said comparator circuit for supplying said output direct currentsignal, said circuit having respective bit circuits; means forsuccessively setting respective bit circuits of said digital-to-analogconversion circuit with set pulses synchronizing with said alternatingsignals, means for producing timing signals for a specific short periodin the vicinity of the peak value of said signal in synchronism withsaid alternating signal, a logic circuit group provided in accordancewith said respective bit circuits and coupled thereto, each of saidlogic circuit having an input circuit coupled to said means forproducing timing signals for said timing signal to be impressed int-osaid logic circuit, an input lead line coupled -to said comparatorcircuit for the output signal of said comparator circuit to be appliedto said logic circuit and an output lead line from said logic circuit,and means for controlling said bit circuits with the output signals ofsaid logic circuits, whereby every one bit of the digital-to-analogconversion is successively compared to be digitized every cycle of theinput alternating signal.

(References 011 following page) 7 v 8 References Cit'ed ,3,019;426 1/1962 Gilbert 340-347 UNITED STATES PATENTS 231 5 2 f g f 2,845,5977/1953 Perkins 324-103 f mmme" 2,865,564 12/1958 Kaiser 340-447 5MAYNARD WILBUR, Exammer- 2, 1/1961 Towles "-5 3 0-347 A. L. NEWMAN, W.KOPACZ, Assistant Examiners.

1. AN ANALOG-TO-DIGITAL CONVERSION SYSTEM COMPRISING A SHIFT-REGISTERCIRCUIT FOR SUCCESSIVELY PRODUCING SET PULSES UPON IMPRESSION OF CLOCKPULSES SYNCHRONIZED WITH INPUT ALTERNATING SIGNALS, A SOURCE OF THEINPUT ALTERNATING SIGNALS, A DIGITAL-TO-ANALOG CONVERSION CIRCUITCOUPLED TO SAID SHIFT-REGISTER CIRCUIT FOR SUCCIVELY PRODUCING DIRECTCURRENT REFERENCES VOLTAGES IN RESPONSE TO THE WEIGHT OF SAID SETPULSES, A COMPARATOR CIRCUIT COUPLED TO SAID SOURCE AND SAID CONVERSIONCIRCUIT FOR DIRECTLY COMPARING SAID DIRECT CURRENT REFERENCE VOLTAGEWITH THE PEAK VALUE OF SAID INPUT ALTERNATING SIGNAL, A GATE CIRCUITCOUPLED TO SAID COMPARATOR CIRCUIT AND TO SAID SOURCE TO THE INPUTALTERNATING SIGNALS TO BE CONTROLLED BY THE OUTPUT SIGNAL OF SAIDCOMPARATOR CIRCUIT, AND MEANS COUPLED BETWEEN SAID GATE CIRCUIT AND SAIDCONVERSION CIRCUIT FOR RE-CONTROLLING SAID DIGITAL-TO-ANALOG CONVERSIONCIRCUIT WITH OUTPUT SIGNAL OF SAID GATE CIRCUIT.